1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor structure. More particularly, the process includes formation of a trench region for device isolation.
2. Description of Related Art
One of methods for forming a trench device isolation region has been disclosed in Japanese Unexamined Patent Publication No. HEI 9(1997)-153543. This conventional art is explained with reference to FIG. 2.
First, a trench 32 is formed in a predetermined width and depth to a predetermined location on the surface of a silicon wafer 31 by use of a photolithography process (FIG. 2(a)). Next, the resulting surface of the silicon wafer 31 is covered with a silicon oxide film 33. This step is for filling the trench 32 with the silicon oxide film 33 and also covering the entire surface of the silicon wafer 31 with the silicon oxide film 33 of a predetermined thickness (FIG. 2(b)).
The surface of the silicon oxide film 33 is flattened (FIG. 2(c)) by chemical mechanical polishing using a slurry containing cerium oxide (CeO.sub.2). Further, the flattened silicon oxide film is polished with use of an abrasive slurry containing fumed silica so as to expose the surface of the silicon wafer 31 (FIG. 2(d)). The ending of chemical mechanical polishing in this case can be judged from exposure of the surface of silicon wafer 31, which is hydrophobic.
Next, the surface of the silicon wafer is subjected to finishing polish with use of an abrasive slurry of silicon compound containing an amine. As a result, a silicon wafer can be obtained which has a trench-isolated structure having a flat silicon surface and an isolation region of a silicon oxide film with rounded corners, but no dishing (FIG. 2(e)).
Thus, in the case where the trench device isolation region embedded with the silicon oxide film is formed by the method of polishing with use of the cerium oxide-containing abrasive slurry and then polishing with use of the fumed silica-containing abrasive slurry, as disclosed by the above-mentioned Japanese Unexamined Patent Publication No. HEI 9(1997)-153543, fumed silica is used for polishing the silicon oxide film to expose the surface of silicon in an active region. However, since the fumed silica has a small selective ratio for a silicon wafer with respect to silicon oxide film, silicon of wafer cannot serve as a polish stopper. For this reason, the surface of silicon is over-polished, which results in a decrease in the depth of the trench.